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PI6C2504A
Phase-Locked Loop Clock Driver with 4 Clock Outputs
Product Features
* High-Performance Phase-Locked-Loop Clock Distribution for Networking * Registered DIMM Synchronous DRAM modules for server/workstation/PC applications * Allows Clock Input to have Spread Spectrum modulation for EMI reduction * Zero Input-to-Output delay * Low jitter: Cycle-to-Cycle jitter 75ps max. * On-chip series damping resistor at clock output drivers for low noise and EMI reduction * Operates at 3.3V VCC * Wide range of Clock Frequencies 80 to 134 MHz * Package: Plastic 16-pin QSOP Package (Q)
Product Description
The PI6C2504A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero.
Logic Block Diagram
G 4 PLL FB_IN AVCC FB_OUT Y[0:3]
Product Pin Configuration
AGND VCC Y0 Y1 GND
1 2 3 4 5 6 7 8
16 15 14
CLK_IN AVCC GND GND Y3 Y2 VCC FB_IN
CLK_IN
16-Pin Q
13 12 11 10 9
Functional Table
Inputs G L H Y[0:3] L CLK _IN Outputs FB_O UT CLK _IN CLK _IN
VCC G FB_OUT
1
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PI6C2504A Phase-Locked Loop Clock Driver with 4 Clock Outputs
Pin Functions
Pin Name CLK _IN FB_IN G FB_O UT Y[0:3] AVC C AGND VC C GND
Pin No. 16 9 7 8 3,4,11,12 15 1 2, 6, 10 5, 13, 14
Type I I I O O Power Ground Power Ground
D e s cription Reference Clock input. CLK _IN allows spread spectrum clock input. Feedback input. FB_IN provides the feedback signal to the internal PLL. O utput bank enable. When G is LO W, outputs Y[0:3] are disabled to a logic low state. Feedback output. FB_O UT is dedicated for external feedback. FB_O UT has an embedded series- damping resistor of the same value as the clock outputs Yx. C lock outputs. These outputs provide low- skew copies of CLK _IN Each output has an embedded series- damping resistor. Analog power supply. For test purposes, AVC C can be also used to bypass the PLL. When AVC C is strapped to ground, PLL is bypassed and CLK _IN is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply. Ground
DC Specifications (Absolute maximum ratings over operating free-air temperature range)
Symbol VI VO VI_DC IO_DC Power TSTG Parame te r Input voltage range Output voltage range DC input voltage DC output current Maximum power dissipation at TA = 55oC in still air Storage temperature 65 0.5 M in. M ax. VCC +0.5 3.8 100 1.0 150 mA W
oC
Units
V
Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parame te r ICC CI CO
Te s t Conditions VI = VCC or GND; IO = 0(1) Standby Current VI = VCC or GND VO =VCC or GND
VCC 3.6V 3.3V
M in.
Typ. 4 6
M ax. 10
Units A pF
Note: 1. Continuous Output Current
Recommended Operating Conditions
Symbol VCC VIH VIL VI TA Supply voltage High level input voltage Low level input voltage Input voltage Operating free- air temperature 0 0 Parame te r M in. 3.0 2.0 0.8 VCC 70 C
PS8501 10/02/00
M ax. 3.6
Units
V
2
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PI6C2504A Phase-Locked Loop Clock Driver with 4 Clock Outputs
Electrical Characteristics (Over Recommended Operating Free-Air Temperature Range
Pull Up/Down Currents of PI6C2504A, VCC = 3.0V)
Symbol IOH
Parame te r Pull- up current Pull- up current Pull- down current Pull- down current
Condition Vout = 2.4V Vout = 2.0V Vout = 0.8V Vout = 0.55V
M in.
M ax. 13.6 22
Units
IOL
19 13
mA
AC Specifications
Symbol FCLK DCYI
(Timing requirements over recommended ranges of supply voltage and operating free-air temperature)
Parame te r Clock frequency PI6C2504A Input clock duty cycle Stabilization Time after power up
M in. 80 40
M ax. 134 60 1
Units MHz % ms
Switching Characteristics
Parame te r tphase error without jitter Jitter, cycle- to- cycle Duty cycle tr, rise- time, 0.4V to 2.0V tf, fall- time, 2.0V to 0.4V
(Over recommended ranges of supply voltage and operating free-air temperature, CL = 30pF)
From (Input) CLK_IN at 100 & 66 MHz At 100 & 66 MHz
To (Output) FB_IN
VCC = 3.3V 0.3V, 0-70C M in. 150 75 45 1.0 1.1 Typ. M ax. +150 +75 55
Units ps % ns
CLK_OUT
Note: These switching parameters are guaranteed by design.
3
PS8501
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PI6C2504A Phase-Locked Loop Clock Driver with 4 Clock Outputs
Package Mechanical Information: 16-pin QSOP Package (Q).
Ordering Information
Orde ring Code PI6C2504AQ Package Name Q16 Package Type 16- pin QSO P Ope rating Range Commercial
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
4
PS8501 10/02/00

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